Analog Circuits: Filters, Amplifiers and Feedback, Op-amps, Oscillators and Timers, Converters and SMPS
1. Analog filters
A first-order RC low-pass filter, output across the capacitor, has H(jω) = 1/(1 + jωRC): unity gain at DC, −3 dB and −45° at the cut-off f_c = 1/(2πRC), and a roll-off of −20 dB per decade above it. With R = 1 kΩ and C = 1 μF, f_c ≈ 159 Hz. Taking the output across the resistor gives the high-pass filter, jωRC/(1 + jωRC), with the same f_c. A band-pass filter passes a band around a centre f₀ with bandwidth B and quality factor Q = f₀/B; a band-reject (notch) filter removes a band, typically mains hum. An nth-order filter rolls off at 20n dB/decade; the Butterworth response is maximally flat in the passband, Chebyshev trades ripple for a steeper edge.
Active filters put the RC network around an op-amp, so the filter can have gain, a low output impedance and no inductors; stages cascade without loading each other, and a second-order stage (the Sallen–Key or multiple-feedback topology) sets its Q with resistor ratios. Before an ADC, a low-pass anti-aliasing filter removes everything above half the sampling rate.
2. Amplifiers: biasing, small-signal model, frequency response and feedback
A transistor amplifier first needs a stable operating point: voltage-divider bias with an emitter resistor fixes I_C largely independently of β and temperature, through the negative feedback of the emitter resistor. Around that point the BJT is linearised to its small-signal model: transconductance g_m = I_C/V_T (V_T = kT/q ≈ 26 mV at room temperature), input resistance r_π = β/g_m, and a common-emitter gain of about −g_m R_C. The frequency response has a low cut-off set by the coupling and bypass capacitors and a high cut-off set by the device capacitances, the collector–base one multiplied by the Miller effect; the gain is flat in between.
Negative feedback trades gain for everything else. With forward gain A and feedback fraction β, A_f = A/(1 + Aβ), and when Aβ ≫ 1, A_f ≈ 1/β, set by the resistors rather than the transistor. The desensitivity 1 + Aβ also widens the bandwidth by the same factor for a single-pole amplifier (gain × bandwidth is conserved) and cuts distortion. A = 1000 and β = 0.099 give 1 + Aβ = 100, A_f = 10, and a 10 kHz open-loop bandwidth becomes 1 MHz. How the feedback is sampled and mixed sets the impedances: series mixing raises the input impedance and shunt mixing lowers it; voltage sampling lowers the output impedance and current sampling raises it.
3. Operational amplifiers: characteristics and applications
The ideal op-amp has infinite open-loop gain, infinite input impedance, zero output impedance and infinite bandwidth, so with negative feedback its inputs draw no current and sit at the same voltage — the virtual short. That gives every standard circuit in one line.
| Circuit | Output |
|---|---|
| Inverting amplifier | v_o = −(R_f/R_i) v_i |
| Non-inverting amplifier | v_o = (1 + R_f/R_i) v_i |
| Voltage follower | v_o = v_i (unity gain, buffer) |
| Summing (inverting) | v_o = −R_f(v₁/R₁ + v₂/R₂ + …) |
| Difference amplifier (matched ratios) | v_o = (R_f/R_i)(v₂ − v₁) |
| Integrator | v_o = −(1/RC) ∫ v_i dt |
| Differentiator | v_o = −RC dv_i/dt |
Real op-amps depart from the ideal in ways GATE quantifies. The gain–bandwidth product is constant: a 1 MHz op-amp set to a non-inverting gain of 20 has a closed-loop bandwidth of 50 kHz. The slew rate limits how fast the output can change, so a sine of peak V_p is undistorted only up to f_max = SR/(2πV_p) — for 0.5 V/μs and 10 V peak, about 7.96 kHz. Input offset voltage and bias currents cause DC errors, and the CMRR measures how well a differential stage rejects a voltage common to both inputs.
4. Oscillators, VCOs and timers, Schmitt triggers, sample and hold
An oscillator is an amplifier with positive feedback that satisfies the Barkhausen criterion at one frequency: loop gain magnitude 1 and total phase shift 0° (or 360°). The RC phase-shift oscillator uses three RC sections for 180° plus an inverting amplifier, oscillating at f = 1/(2πRC√6) with a gain of at least 29; the Wien-bridge oscillator uses a lead–lag network with zero phase at f = 1/(2πRC), where it passes one third, so the amplifier needs a gain of 3. LC (Colpitts, Hartley) oscillators serve at radio frequencies, and crystal oscillators give the stable clocks of every microcontroller. A voltage-controlled oscillator makes its frequency proportional to a control voltage — the heart of a phase-locked loop and of voltage-to-frequency conversion.
The 555 timer compares a capacitor voltage with 1/3 and 2/3 of the supply. As a monostable it gives one pulse of T = 1.1RC; as an astable it oscillates at f = 1.44/((R_A + 2R_B)C) with duty cycle (R_A + R_B)/(R_A + 2R_B) — for R_A = 1 kΩ, R_B = 10 kΩ, C = 0.1 μF, about 686 Hz and 52%. A Schmitt trigger is a comparator with positive feedback: two thresholds, ±βV_sat for a feedback fraction β, and the gap between them, the hysteresis, keeps a noisy slowly-varying input from making the output chatter. A sample-and-hold captures a voltage on a capacitor and holds it still for the ADC: its acquisition time is how long it needs to charge, its aperture time the uncertainty in when it switches to hold, and its droop the rate at which leakage bleeds the held voltage, I/C.
5. A/D and D/A converters, and switched-mode power supplies
An n-bit converter divides its full-scale range into 2ⁿ steps of 1 LSB = V_FS/2ⁿ: 20 mV for 8 bits over 5.12 V. An ideal ADC that rounds has a quantisation error of ±½ LSB, and its signal-to-noise ratio for a full-scale sine is about 6.02n + 1.76 dB. A DAC gives V_out = V_ref × D/2ⁿ for the input code D — the R–2R ladder does it with only two resistor values, where the binary-weighted DAC needs a span of 2ⁿ⁻¹. The ADC architectures trade speed for resolution.
| Type | How it converts | Character |
|---|---|---|
| Flash | 2ⁿ − 1 comparators in parallel | Fastest; comparator count doubles per bit |
| Successive approximation | Binary search, one bit per clock: n clocks | The microcontroller workhorse |
| Dual-slope integrating | Integrate input for a fixed time, de-integrate with reference | Slow; rejects noise; R and C cancel out of the result |
| Sigma–delta | Oversample with a 1-bit loop, then digitally filter | High resolution at modest speed |
A switched-mode power supply chops the input with a transistor switch at tens or hundreds of kilohertz and filters the result with an inductor and capacitor, so the switch is either fully on or fully off and little power is lost — efficiencies of 80–95% against a linear regulator’s V_out/V_in. In steady state, with duty ratio D: the buck converter gives V_o = D V_in (24 V at D = 0.25 gives 6 V); the boost gives V_o = V_in/(1 − D) (12 V at D = 0.6 gives 30 V); the buck–boost gives an inverted D/(1 − D) V_in. Flyback and forward converters add a transformer for isolation.
Key takeaways
- First-order RC: f_c = 1/(2πRC), −3 dB and 20 dB/decade; nth order rolls off at 20n dB/decade; Q = f₀/B for a band-pass.
- A_f = A/(1 + Aβ) ≈ 1/β; negative feedback widens bandwidth by 1 + Aβ; series mixing raises input impedance, voltage sampling lowers output impedance.
- Inverting −R_f/R_i, non-inverting 1 + R_f/R_i; closed-loop bandwidth = GBW/gain; slew-rate limit f_max = SR/(2πV_p).
- Barkhausen: loop gain 1, phase 0°; Wien bridge needs gain 3; 555 astable f = 1.44/((R_A + 2R_B)C); a Schmitt trigger’s hysteresis rejects noise.
- LSB = V_FS/2ⁿ, error ±½ LSB; flash is fastest with 2ⁿ − 1 comparators, SAR takes n clocks; buck D V_in, boost V_in/(1 − D).
Practice questions (15)
Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.
A first-order RC low-pass filter has R = 1 kΩ and C = 1 μF. Its cut-off frequency, to the nearest hertz, is ____ Hz.
Numerical answer — type the value.
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Answer: 159
f_c = 1/(2πRC) = 1/(2π × 10⁻³) ≈ 159.2 Hz. 1/(RC) = 1000 is the cut-off in rad/s; forgetting the 2π reports it in hertz.Well above its cut-off frequency, the gain of a second-order low-pass filter falls at:
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Answer: A — 40 dB per decade
Each pole contributes −20 dB/decade (−6 dB/octave), so two poles give −40 dB/decade. 6 dB is the per-octave figure of a first-order filter.An amplifier with open-loop gain 1000 is given negative feedback with feedback fraction β = 0.099. The closed-loop gain is ____.
Numerical answer — type the value.
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Answer: 10
A_f = A/(1 + Aβ) = 1000/(1 + 99) = 10. The approximation 1/β ≈ 10.1 is close because Aβ = 99 is large; using 1 − Aβ in the denominator is positive feedback.An amplifier has a single-pole open-loop gain of 1000 with an open-loop bandwidth of 10 kHz, and is given negative feedback with feedback fraction β = 0.099. Its closed-loop bandwidth is ____ kHz.
Numerical answer — type the value.
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Answer: 1000
For a single pole the bandwidth rises by the same factor the gain falls, 1 + Aβ = 100: 10 kHz × 100 = 1000 kHz (1 MHz). The gain–bandwidth product 1000 × 10 kHz = 10 × 1 MHz is conserved.An ideal op-amp is used as a non-inverting amplifier with R_i = 2 kΩ (to ground) and R_f = 18 kΩ. For an input of 0.25 V the output is ____ V.
Numerical answer — type the value.
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Answer: 2.5
Gain = 1 + R_f/R_i = 1 + 9 = 10, so v_o = 2.5 V. The inverting formula would give −9 × 0.25 = −2.25 V.An op-amp has a slew rate of 0.5 V/μs. The highest frequency at which it can deliver an undistorted sinusoid of 10 V peak, correct to two decimal places, is ____ kHz.
Numerical answer — type the value.
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Answer: 7.96
The steepest slope of V_p sin ωt is ωV_p, so ωV_p ≤ SR: f_max = SR/(2πV_p) = 0.5 × 10⁶/(2π × 10) ≈ 7958 Hz = 7.96 kHz. Omitting the 2π gives 50 kHz.An op-amp with a gain–bandwidth product of 1 MHz is configured as a non-inverting amplifier of gain 20. Its closed-loop bandwidth is ____ kHz.
Numerical answer — type the value.
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Answer: 50
Bandwidth = GBW/closed-loop (noise) gain = 1 MHz/20 = 50 kHz. For a non-inverting stage the noise gain equals the signal gain, 1 + R_f/R_i.A Wien-bridge oscillator sustains oscillation when the gain of its amplifier is:
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Answer: A — 3
At f = 1/(2πRC) the lead–lag network has zero phase shift and passes one third of the output, so a loop gain of 1 needs an amplifier gain of 3. 29 is the RC phase-shift oscillator’s requirement.A 555 timer in astable mode has R_A = 1 kΩ, R_B = 10 kΩ and C = 0.1 μF. Taking f = 1.44/((R_A + 2R_B)C), its output frequency, to the nearest hertz, is ____ Hz.
Numerical answer — type the value.
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Answer: 686
f = 1.44/((R_A + 2R_B)C) = 1.44/(21 × 10³ × 10⁻⁷) = 1.44/(2.1 × 10⁻³) ≈ 685.7 Hz, so 686 Hz, with duty cycle 11/21 ≈ 52%. Using R_A + R_B gives 1309 Hz.The main purpose of the hysteresis in a Schmitt trigger is to:
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Answer: A — prevent multiple output transitions when a slow, noisy input crosses the threshold
With two thresholds, once the output switches the input must move back past the other threshold before it switches again, so noise smaller than the hysteresis band cannot make it chatter. The circuit is a switching comparator, not a linear amplifier.An 8-bit ADC has a full-scale input range of 0 to 5.12 V. Its resolution (1 LSB) is ____ mV.
Numerical answer — type the value.
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Answer: 20
1 LSB = V_FS/2ⁿ = 5.12/256 = 0.02 V = 20 mV. Dividing by 255 gives 20.08 mV, the convention some texts use for the code-to-code spacing when the top code equals full scale.Which ADC architecture gives the fastest conversion?
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Answer: A — Flash
A flash ADC compares the input with all 2ⁿ − 1 levels at once and converts in a single step, at the price of exponentially many comparators. SAR needs n steps; integrating and counter types are slower still.An ideal boost converter operating in continuous conduction has an input of 12 V and a duty ratio of 0.6. Its output voltage is ____ V.
Numerical answer — type the value.
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Answer: 30
V_o = V_in/(1 − D) = 12/0.4 = 30 V. D × V_in = 7.2 V is the buck relation, and a boost converter cannot step down.Which are characteristics of an ideal op-amp?
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Answer: A — Infinite open-loop voltage gain; B — Infinite input impedance; C — Zero output impedance
The ideal op-amp has infinite gain, infinite input impedance, zero output impedance and infinite bandwidth, with zero offset. Zero bandwidth would mean it amplified nothing but DC; real op-amps have a finite gain–bandwidth product.Which statements about data converters are true?
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Answer: A — An n-bit successive-approximation ADC needs n clock cycles per conversion; B — An n-bit flash ADC needs 2ⁿ − 1 comparators; D — The quantisation error of an ideal rounding ADC is within ±½ LSB
(A) One bit is decided per clock, MSB first. (B) One comparator per threshold between the 2ⁿ levels. (C) False: the dual-slope integrates for a fixed period and then de-integrates — milliseconds per conversion, the slowest common type. (D) Rounding to the nearest level errs by at most half a step.