Embedded Systems: Microprocessors and Microcontrollers, Timers, Interrupts, Memory and I/O Interfacing, Data Acquisition

The second paragraph of Section B1.1 names microprocessor and microcontroller applications; the components of a microcontroller — CPU, memory, I/O ports and timers; interrupt handling; memory and input–output interfacing; and the basics of data acquisition systems. This is the computer inside every robot joint controller, PLC and drive. GATE asks it as arithmetic on addresses, timer counts and data rates, and as what a processor does when an interrupt arrives; each is worked here.

1. Microprocessors, microcontrollers and their components

A microprocessor is a CPU on a chip; a system built on it adds external memory, I/O and timer chips on a bus, and suits general computing. A microcontroller puts the CPU, program memory (flash), data memory (RAM, often EEPROM), I/O ports, timers/counters, an ADC and serial interfaces on one chip, and suits dedicated control — a motor drive, a sensor node, a joint controller. The CPU has an ALU, registers, a program counter holding the address of the next instruction and a stack pointer for calls and interrupts. The Harvard architecture gives program and data separate memories and buses, so an instruction can be fetched while data is accessed; the von Neumann architecture shares one.

I/O ports are pins grouped into registers, each pin set as input or output by a direction register; reading the input register samples the pins and writing the output register drives them. A watchdog timer resets the processor unless the software restarts it regularly, recovering a program that has hung. Serial interfaces carry data in few wires: UART (asynchronous, start and stop bits), SPI (synchronous, full duplex, clock, MOSI, MISO and a slave-select per device) and I²C (two open-drain lines, SDA and SCL, with pull-ups and addressed devices).

2. Timers and counters

A timer is a counter clocked by the system clock through a prescaler; a counter is the same hardware clocked by an external pin. An n-bit timer overflows after 2ⁿ ticks, and each tick lasts prescaler/f_clk. At 16 MHz with a prescaler of 64 the tick is 4 μs, so an 8-bit timer overflows every 256 × 4 = 1024 μs and a 16-bit one every 262.144 ms; a 1 ms period needs 250 ticks. To get a period of N ticks from an overflow, preload the timer with 2ⁿ − N: a 16-bit timer ticking at 1 MHz reaches a 10 ms overflow from 65536 − 10000 = 55536. Compare units raise an event when the count matches a register, and generate PWM: in an 8-bit PWM whose duty is the compare value over 256, a value of 64 gives 25%. Capture units latch the count on an external edge, to time pulses or measure encoder speed.

3. Interrupt handling

Polling checks a device in a loop and wastes time; an interrupt lets the device signal the CPU. On an interrupt the CPU finishes the current instruction, saves the program counter (and status) on the stack, looks up the interrupt vector for that source and jumps to its interrupt service routine; the ISR saves any registers it uses, services the device, clears the flag, and returns, restoring the saved state. Sources have priorities, and a higher-priority interrupt may nest inside a lower one. Maskable interrupts can be disabled by software; a non-maskable interrupt cannot, and is kept for emergencies such as power failure. External interrupts are edge- or level-triggered; the latency is the time from the request to the first ISR instruction.

⚠️ Keep the ISR short
An ISR that waits in a delay loop blocks every lower-priority interrupt for that time. Set a flag or move data to a buffer and do the work in the main loop; declare variables shared with the ISR volatile, and read multi-byte shared variables with interrupts briefly disabled so the ISR cannot change them half-way through.

4. Memory and input–output interfacing

A memory of 2ᵏ locations needs k address lines: 8 KB needs 13, 64 KB needs 16. Chips smaller than the address space are placed by address decoding: the high address lines drive a decoder whose outputs are the chips’ chip-select inputs, and the low lines go to every chip. 64 KB built from 8 KB chips needs 8 chips, the 13 low lines to each and the top 3 lines to a 3-to-8 decoder. A chip’s address range is its base plus its size less one: 2 KB (800H) starting at 8000H ends at 87FFH. Full decoding uses every address line and gives each location one address; partial decoding ignores some, is cheaper, and makes the chip appear at several aliased addresses.

I/O devices are reached either as memory-mapped I/O, occupying addresses in the memory space and used with ordinary load and store instructions, or as I/O-mapped (isolated) I/O, in a separate port space with IN and OUT instructions and a control line that distinguishes the two. Serial rates follow from the frame: a UART at 9600 baud sending 8 data bits with one start and one stop bit (8N1) moves 10 bits per character, so 960 characters per second.

5. Data acquisition systems

A data acquisition system takes signals from the plant to the processor: sensor → signal conditioning (amplify, filter) → anti-aliasing filter → analog multiplexer → sample-and-hold → ADC → processor or memory, often with DMA moving samples without the CPU. Multiplexing N channels into one ADC of rate f_s gives each channel f_s/N, and by the sampling theorem each can then carry frequencies only below f_s/(2N): eight channels on a 100 kS/s ADC get 12.5 kS/s each and a 6.25 kHz limit. The ADC’s resolution sets the smallest change seen, and its conversion time with the multiplexer’s settling sets the throughput.

Key takeaways

  • A microcontroller integrates CPU, flash, RAM, I/O ports, timers, ADC and serial ports; Harvard separates program and data memory.
  • Tick = prescaler/f_clk; an n-bit timer overflows after 2ⁿ ticks; preload 2ⁿ − N for a period of N ticks.
  • On an interrupt the PC is saved and the vector selects the ISR; NMIs cannot be masked; keep ISRs short and shared variables volatile.
  • 2ᵏ locations need k address lines; high lines drive the chip-select decoder; memory-mapped I/O uses memory instructions.
  • UART 8N1 sends 10 bits per character; a DAQ multiplexing N channels at f_s gives each f_s/N and a signal limit of f_s/(2N).

Practice questions (14)

Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.

  1. In the Harvard architecture:

    1. program and data are held in separate memories with separate buses
    2. program and data share one memory and one bus
    3. there is no program counter
    4. all instructions are the same length by definition
    Show answer

    Answer: A — program and data are held in separate memories with separate buses

    Separate program and data paths let an instruction be fetched while data is read or written, which is why most microcontrollers use it. Sharing one memory and bus is the von Neumann architecture; fixed instruction length is a RISC trait, not Harvard’s.

  2. The number of address lines needed to address every byte of an 8 KB memory is ____.

    Numerical answer — type the value.

    Show answer

    Answer: 13

    8 KB = 8192 = 2¹³ bytes, so 13 lines. 8 lines address only 256 locations; 16 lines address 64 KB.

  3. A 2 KB ROM is mapped into a 16-bit address space starting at 8000H. Its last address is:

    1. 87FFH
    2. 8FFFH
    3. 83FFH
    4. 8800H
    Show answer

    Answer: A — 87FFH

    2 KB = 2048 = 800H locations, so the last address is 8000H + 800H − 1 = 87FFH. 8FFFH would span 4 KB, 83FFH 1 KB, and 8800H is the first address after the chip.

  4. A microcontroller runs at 16 MHz and an 8-bit timer is clocked through a prescaler of 64. The time between overflows of the timer is ____ μs.

    Numerical answer — type the value.

    Show answer

    Answer: 1024

    Tick = 64/16 MHz = 4 μs, and an 8-bit timer overflows every 2⁸ = 256 ticks: 1024 μs. Using 255 ticks gives 1020 μs; a 16-bit timer would take 262 144 μs.

  5. A 16-bit up-counting timer is clocked at 1 MHz (after its prescaler) and interrupts on overflow from FFFFH to 0000H. To obtain an interrupt every 10 ms, the value to reload into the timer after each overflow, in decimal, is ____.

    Numerical answer — type the value.

    Show answer

    Answer: 55536

    10 ms at 1 μs per tick is 10 000 ticks, and the timer overflows after reaching 65 536 counts, so start it at 65 536 − 10 000 = 55 536. Loading 10 000 would give 55 536 ticks, about 55.5 ms.

  6. When a microcontroller accepts an interrupt, it first:

    1. completes the current instruction, saves the program counter and jumps to the service routine given by the interrupt vector
    2. abandons the current instruction and restarts the program from reset
    3. disables all interrupts permanently
    4. waits until the main program finishes
    Show answer

    Answer: A — completes the current instruction, saves the program counter and jumps to the service routine given by the interrupt vector

    Saving the return address lets the ISR run and the interrupted program resume exactly where it stopped. Restarting from reset is what a watchdog does, not an interrupt; interrupts are usually disabled only for the duration of entry, not permanently.

  7. A non-maskable interrupt is one that:

    1. cannot be disabled by software
    2. has the lowest priority
    3. can be triggered only by software
    4. is always level-triggered
    Show answer

    Answer: A — cannot be disabled by software

    A non-maskable interrupt bypasses the interrupt-enable mask, so it is reserved for events that must never be ignored, such as imminent power failure; it usually has the highest priority, not the lowest.

  8. Which are good practice when writing interrupt service routines?

    1. Keep the ISR short, deferring heavy work to the main loop
    2. Declare variables shared with the main program volatile
    3. Use long blocking delays inside the ISR
    4. Protect multi-byte shared variables from being changed half-way through a read in the main program
    Show answer

    Answer: A — Keep the ISR short, deferring heavy work to the main loop; B — Declare variables shared with the main program volatile; D — Protect multi-byte shared variables from being changed half-way through a read in the main program

    (A) A long ISR delays every other interrupt. (B) volatile stops the compiler caching a value the ISR can change. (C) False: a blocking delay inside an ISR stalls the system. (D) Otherwise the main loop can read half an old value and half a new one.

  9. A UART transmits at 9600 baud with 8 data bits, no parity, one start bit and one stop bit. The maximum number of characters it can send per second is ____.

    Numerical answer — type the value.

    Show answer

    Answer: 960

    Each character frame is 1 + 8 + 1 = 10 bits, so 9600/10 = 960 characters per second. Dividing by 8 counts only the data bits and gives 1200.

  10. The I²C bus uses:

    1. two lines, serial data (SDA) and serial clock (SCL)
    2. four lines, MOSI, MISO, SCLK and SS
    3. one line with no clock
    4. a parallel 8-bit data bus
    Show answer

    Answer: A — two lines, serial data (SDA) and serial clock (SCL)

    I²C runs addressed devices on two open-drain lines with pull-up resistors. The four-line set is SPI; a single line with no clock describes UART-style asynchronous links.

  11. In memory-mapped I/O:

    1. I/O devices occupy addresses in the memory space and are accessed with ordinary memory instructions
    2. I/O devices have a separate address space reached only by IN and OUT instructions
    3. I/O devices cannot generate interrupts
    4. memory must be accessed through the I/O ports
    Show answer

    Answer: A — I/O devices occupy addresses in the memory space and are accessed with ordinary memory instructions

    Memory-mapped I/O gives device registers memory addresses, so every addressing mode works on them, at the cost of some address space. A separate space with IN and OUT is I/O-mapped (isolated) I/O.

  12. A data acquisition system multiplexes 8 analog channels into a single ADC that converts 100 000 samples per second, sampling the channels in turn. Ignoring filter roll-off, the highest signal frequency each channel can carry without aliasing is ____ kHz.

    Numerical answer — type the value.

    Show answer

    Answer: 6.25

    Each channel is sampled at 100 000/8 = 12 500 samples/s, and the sampling theorem allows frequencies below half of that: 6.25 kHz. Halving the ADC’s full rate gives 50 kHz and forgets that the channels share it.

  13. Which statements comparing microcontrollers and microprocessors are true?

    1. A microcontroller integrates the CPU, memory, I/O ports and timers on one chip
    2. Microcontrollers are designed chiefly for general-purpose personal computers rather than embedded control
    3. A microprocessor-based system needs external memory and I/O devices
    4. A watchdog timer resets the processor if the software stops restarting it
    Show answer

    Answer: A — A microcontroller integrates the CPU, memory, I/O ports and timers on one chip; C — A microprocessor-based system needs external memory and I/O devices; D — A watchdog timer resets the processor if the software stops restarting it

    (A) The defining integration. (B) False: that describes microprocessors; microcontrollers target dedicated embedded control. (C) The CPU chip alone has no program memory or ports. (D) A hung program stops servicing the watchdog, which then forces a reset.

  14. An 8-bit PWM generator produces a duty cycle equal to its compare value divided by 256. For a compare value of 64 the duty cycle is ____ %.

    Numerical answer — type the value.

    Show answer

    Answer: 25

    64/256 = 0.25 = 25%. The average output of such a PWM into a filter or motor is 25% of the supply.