Computer Knowledge I: Hardware, Memory, Operating Systems, Databases and Networks
Inside the CPU: Registers, Buses and the Instruction Cycle
The CPU repeats one loop for every instruction: fetch (bring the instruction from memory), decode (the control unit works out what it means) and execute (the ALU or another unit does it), then the result is stored. The loop is driven by a clock; its speed is measured in hertz (GHz means billions of cycles per second). A processor with several cores can run several instruction streams at once.
| Register | Holds |
|---|---|
| Program Counter (PC) | Address of the next instruction to fetch |
| Instruction Register (IR) | The instruction now being decoded and executed |
| Memory Address Register (MAR) | Address of the memory location to be read or written |
| Memory Data Register (MDR) | The data just read from, or about to be written to, memory |
| Accumulator | Intermediate results of the ALU |
Buses. The data bus carries data and works in both directions. The address bus carries addresses from the CPU towards memory and devices, one way only. The control bus carries command and timing signals such as read and write. The width of the address bus fixes the memory the CPU can reach: with n address lines there are 2ⁿ locations. Example: 16 lines give 2¹⁶ = 65,536 locations, which is 64 KB when each location holds one byte; 20 lines give 2²⁰ = 1,048,576, that is 1 MB.
Memory Hierarchy, Access Methods and Transfer Sums
Going down the hierarchy from registers to tape, speed and cost per bit fall while capacity rises. No device is fast, large and cheap together, so a computer layers them: small fast stores near the CPU hold what is needed now, large slow stores hold the rest. This works because programs reuse recently used data and its neighbours, the idea called locality of reference.
- Sequential access: to reach a record you pass all before it. Magnetic tape is the example, which is why it suits backup and archives, not live work.
- Direct (random) access: the device jumps straight to a location. RAM, hard disks, SSDs and optical discs work this way.
- Flash memory (pen drives, memory cards, SSDs) is non-volatile and has no moving parts. Cloud storage keeps files on a provider's remote servers, reached over the Internet.
Storage against transfer units. Storage is counted in bytes (capital B), line speed in bits per second (small b). Conversion: 1 byte = 8 bits. Worked example: a 15 MB file over a 5 megabit-per-second link, taking 1 MB = 8 megabits and ignoring overhead, needs 15 × 8 = 120 megabits, and 120 ÷ 5 = 24 seconds. Dividing 15 by 5 and getting 3 seconds is the usual slip.
Operating Systems: Types, Functions and Terms
| Type | Idea |
|---|---|
| Batch | Similar jobs are collected and run one after another with no user interaction |
| Time-sharing / multitasking | The CPU switches rapidly so many users or tasks seem to run together |
| Multiprocessing | More than one CPU in one machine share the work |
| Real-time | Guarantees a response within a fixed deadline: flight control, industrial robots |
| Distributed | Many networked computers act as one system to the user |
Terms. The kernel is the core that controls hardware, memory and processes; the shell is the layer that takes the user's commands and passes them to the kernel. Booting loads the OS: a cold boot starts from power-off, a warm boot restarts without cutting power. Spooling (Simultaneous Peripheral Operations On-Line) stores output in a buffer so a slow printer does not hold up the CPU. Paging divides memory into fixed-size blocks (pages and frames), whereas segmentation uses variable-size parts. Virtual memory borrows disk space to run programs larger than RAM; if the system spends most of its time swapping pages in and out, the condition is thrashing. A device driver lets the OS talk to a particular device.
Scheduling and deadlock. FCFS serves in order of arrival; SJF (shortest job first) gives the least average waiting time when all jobs arrive together; Round Robin gives each process a fixed time quantum in turn. Worked example: jobs of 6, 3 and 3 ms arrive together. Under FCFS the waits are 0, 6 and 9, average 5 ms; under SJF (3, 3, 6) the waits are 0, 3 and 6, average 3 ms. A deadlock needs all four conditions together: mutual exclusion, hold and wait, no pre-emption, circular wait.
DBMS: Keys, Normal Forms and SQL Groups
The common course names primary, foreign and candidate keys and the DDL and DML commands. Banking papers add the finer terms. In relational language a table is a relation, a row is a tuple, a column is an attribute. The degree is the number of columns and the cardinality is the number of rows: a table of 6 columns and 40 rows has degree 6 and cardinality 40. A super key is any column set that identifies a row uniquely; a candidate key is a minimal super key; the one chosen is the primary key and each other candidate is an alternate key. A composite key uses more than one column.
| Group | Purpose | Commands |
|---|---|---|
| DDL | Defines structure | CREATE, ALTER, DROP, TRUNCATE |
| DML | Changes the rows | INSERT, UPDATE, DELETE |
| DCL | Controls access rights | GRANT, REVOKE |
| TCL | Controls transactions | COMMIT, ROLLBACK, SAVEPOINT |
Queries and design. WHERE filters rows before grouping, HAVING filters the groups afterwards; ORDER BY sorts and GROUP BY groups. Aggregate functions are COUNT, SUM, AVG, MIN and MAX. The Cartesian product of tables with 4 and 5 rows has 4 × 5 = 20 rows. Normalisation removes redundancy and update anomalies: 1NF needs atomic values; 2NF removes partial dependency (a column depending on only part of a composite key); 3NF removes transitive dependency (a non-key column depending on another non-key column). A transaction follows ACID: Atomicity (all or nothing), Consistency, Isolation and Durability.
Network Layers, Addresses and Transmission
The common course covers topologies, devices and protocol names. The next level is the layered view. The OSI model has seven layers; from the top: Application, Presentation, Session, Transport, Network, Data Link, Physical. The TCP/IP model has four: Application, Transport, Internet, Network Access.
| Layer | Job | Data unit and examples |
|---|---|---|
| Physical | Sends raw bits over the medium | Bits; hub, repeater, cable |
| Data Link | Delivers between neighbouring devices using MAC addresses | Frame; Ethernet switch, bridge |
| Network | Routes using logical (IP) addresses | Packet; router, IP |
| Transport | End-to-end delivery, reliability, ports | Segment; TCP (reliable), UDP (fast, no guarantee) |
| Session, Presentation | Session opens and closes dialogues; presentation translates, compresses, encrypts | Data |
| Application | Services the user's programs use | HTTP, SMTP, FTP, DNS |
IPv4 classes are fixed by the first number: A 1 to 126, B 128 to 191, C 192 to 223, D 224 to 239 (multicast), E 240 to 255 (reserved); 127 is the loopback range. Private ranges, not routed on the public Internet, are 10.0.0.0 to 10.255.255.255, 172.16.0.0 to 172.31.255.255 and 192.168.0.0 to 192.168.255.255. Transmission modes: simplex one way only (keyboard to computer, television broadcast); half duplex both ways but one at a time (walkie-talkie); full duplex both ways together (telephone). Packet switching splits messages into packets that travel independently, as on the Internet; circuit switching reserves a path for the whole call, as in the old telephone network. Optical fibre carries light, has the largest bandwidth and is immune to electrical interference.
Number Codes and Logic Gates
The common course teaches binary, octal and hex conversions. Three further skills are asked. Hex arithmetic: add digit by digit and carry at 16. (A5)₁₆ + (1B)₁₆: 5 + B (11) = 16, write 0 carry 1; A (10) + 1 + 1 = 12 = C; the answer is (C0)₁₆, and 165 + 27 = 192 = 12 × 16 confirms it. Two's complement for negatives in 8 bits: if the leading bit is 1, invert all bits, add 1 and attach a minus sign. Example: 11110100 inverts to 00001011 (11), plus 1 gives 12, so the value is −12. BCD codes each decimal digit in its own 4 bits: 59 is 0101 1001.
| Gate | Output is 1 when | Note |
|---|---|---|
| AND, OR, NOT | both inputs 1; at least one input 1; the input is 0 | Basic gates |
| NAND, NOR | not both inputs are 1; both inputs are 0 | Universal gates: any circuit can be built from either one |
| XOR, XNOR | the inputs differ; the inputs are equal | XNOR is the complement of XOR |
Adders. A half adder adds two bits: Sum = A XOR B and Carry = A AND B. A full adder also takes a carry-in, so it adds three bits: with A = 1, B = 1 and carry-in = 1 the total is 3 = 11 in binary, giving Sum 1, Carry-out 1. Useful laws: A + A·B = A, and De Morgan: the complement of (A·B) is A′ + B′.
Key takeaways
- A supercomputer calculates (FLOPS) and a mainframe handles transactions; the generation follows the switching component, and 4GL is unrelated to the fourth hardware generation.
- PC holds the next instruction's address, IR the current instruction; the data bus is two-way, the address bus one-way; n address lines reach 2^n locations.
- Convert bytes to bits before dividing by a line speed: 24 MB at 4 megabits per second is 48 seconds, not 6.
- Know the OS types, kernel versus shell, spooling, paging, thrashing, the four deadlock conditions (no pre-emption) and how to compute FCFS and Round Robin waits.
- Degree is columns and cardinality is rows; the primary key is one candidate key and the rest are alternate keys; a partial dependency breaks 2NF; TRUNCATE is DDL, GRANT is DCL, COMMIT is TCL.
- OSI has seven layers (frame at Data Link, packet at Network, segment at Transport); 172.16 to 172.31 is private; for logic, a full adder of 1, 1, 1 gives sum 1 and carry 1.
Practice questions (20)
Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.
Which register of the CPU holds the address of the next instruction to be fetched?
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Answer: B — Program Counter
The Program Counter points to the next instruction. The Instruction Register is the tempting alternative, but it holds the instruction already fetched and now being decoded; the Memory Data Register holds data in transit and the accumulator holds ALU results.Consider these statements about CPU buses. P: The data bus carries data in both directions. Q: The address bus carries addresses in both directions between the CPU and memory. R: The control unit performs the arithmetic and logical comparisons. S: The control bus carries command and timing signals. Which statements are correct?
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Answer: A — P and S only
P and S are correct. The address bus is one-way, from the CPU towards memory and devices, so Q is wrong, and arithmetic and logic belong to the ALU, not the control unit, so R is wrong. The pair Q and R is therefore the opposite of the truth.A processor has a 16-bit address bus and each address location holds one byte. What is the largest memory it can address directly?
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Answer: C — 64 KB
Sixteen address lines give 2^16 = 65,536 locations, and 65,536 bytes divided by 1024 is 64 KB. The value 32 KB would need 15 lines and 256 KB would need 18 lines, so neither matches 16 lines.Which of the following pairs a kind of computer with a correct description?
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Answer: D — Supercomputer: built for a few huge calculations, with speed rated in FLOPS
A supercomputer targets giant numerical jobs and its speed is quoted in floating-point operations per second. A mainframe serves many users centrally, an embedded computer runs one fixed program inside a device, and an analog computer measures continuous quantities, so the other three descriptions are wrong.A 24 MB file is sent over a link of 4 megabits per second. Taking 1 byte = 8 bits, 1 MB = 8 megabits and ignoring overhead, how long does the transfer take?
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Answer: B — 48 seconds
24 MB is 24 × 8 = 192 megabits, and 192 ÷ 4 = 48 seconds. The figure 6 seconds comes from dividing megabytes by megabits per second without converting bytes to bits, which is the usual slip.Consider these statements. P: Virtual memory uses part of secondary storage so that programs larger than the available RAM can run. Q: Cache memory is built from DRAM because DRAM is faster than SRAM. R: Thrashing is the condition in which a system spends most of its time swapping pages instead of executing programs. S: Registers are slower than cache memory. Which statements are correct?
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Answer: C — P and R only
P and R are correct. Cache is made of SRAM, which is faster than DRAM, so Q is wrong, and registers sit inside the CPU and are faster than cache, so S is wrong. Hence any option containing Q or S fails.Which of the following is NOT one of the four conditions that must hold together for a deadlock to occur?
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Answer: D — Pre-emption: resources can be forcibly taken back from a process
Deadlock needs the absence of pre-emption: if resources could be taken back, the chain could be broken. So pre-emption being possible is not a condition for deadlock. Mutual exclusion, hold and wait and circular wait are three of the four required conditions.Three processes P1, P2 and P3 arrive together at time 0 with CPU bursts of 5, 3 and 2 ms and join the queue in that order. The system uses Round Robin with a 2 ms time quantum and ignores switching time. What is the average waiting time (completion time minus burst time)?
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Answer: C — 5 ms
The run order is P1 0 to 2, P2 2 to 4, P3 4 to 6 (done at 6), P1 6 to 8, P2 8 to 9 (done at 9), P1 9 to 10 (done at 10). Waits are 10 − 5 = 5, 9 − 3 = 6 and 6 − 2 = 4, total 15, average 5 ms. Plain FCFS would give 13/3 ms, not an option here.Match the terms with their meanings. Terms: P Kernel, Q Shell, R Spooling, S Thrashing. Meanings:
(i) heavy paging with little useful work done;
(ii) the core of the OS that controls hardware and memory;
(iii) the layer that interprets the user's commands;
(iv) buffering output so a slow device does not hold up the CPU.
Which matching is correct?Show answer
Answer: A — P-ii, Q-iii, R-iv, S-i
The kernel is the core (ii), the shell interprets commands (iii), spooling buffers output (iv) and thrashing is heavy paging (i). Swapping kernel and shell (P-iii, Q-ii) is the commonest confusion, and the other matchings misplace spooling or thrashing.In relational terminology, a table STUDENT has 6 columns and 40 rows. What are its degree and cardinality?
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Answer: D — Degree 6 and cardinality 40
Degree is the number of attributes (columns), 6, and cardinality is the number of tuples (rows), 40. Degree 40 and cardinality 6 reverses the two terms, which is the standard trap.A table EMPLOYEE has the columns EmpID, PAN, Email, Name and Dept. EmpID, PAN and Email are each unique and never null for every employee, while Name and Dept values repeat, alone or together. EmpID is chosen as the primary key. How many alternate keys does the table have?
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Answer: B — Two
Candidate keys are EmpID, PAN and Email, because Name and Dept cannot identify a row even together. The primary key takes one, leaving PAN and Email as the two alternate keys. Answering three counts the primary key too.A table ORDER_ITEM has the composite primary key (OrderID, ItemID) and the columns Quantity and ItemName. Quantity depends on the whole key, but ItemName depends only on ItemID. If all values are atomic, which normal form does the table fail first?
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Answer: D — Second normal form
ItemName depends on part of the composite key, a partial dependency, which violates second normal form. First normal form holds because the values are atomic. Third and Boyce-Codd forms are also not satisfied, but the normal forms are checked in order, so the table fails at the second.Consider these statements about SQL. P: GRANT and REVOKE belong to the data control group. Q: ALTER is a data manipulation command. R: ROLLBACK undoes changes that have not yet been committed. S: DROP removes only the rows of a table and keeps the empty table. Which statements are correct?
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Answer: C — P and R only
P and R are correct. ALTER changes structure, so it is a definition command and Q is wrong; DROP deletes the whole table with its structure, whereas keeping the empty table describes DELETE of all rows, so S is wrong.Taking the OSI layers P Transport, Q Network, R Session and S Data Link, which sequence lists them from the lowest layer upward?
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Answer: D — S, Q, P, R
From the bottom the order is Physical, Data Link, Network, Transport, Session, Presentation, Application, so the four given run S, Q, P, R. The option with Transport below Network, or Session below Transport, breaks that order.In the OSI model, which pairing of a layer with the data unit it handles is correct?
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Answer: B — Data Link layer and frame
The Data Link layer handles frames. The Network layer handles packets and the Transport layer handles segments, so pairing Network with segment is the tempting swap; the Physical layer handles raw bits.Which of the following IPv4 addresses lies in a private range that is not routed on the public Internet?
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Answer: A — 172.20.4.5
The private ranges are 10.x.x.x, 172.16.0.0 to 172.31.255.255 and 192.168.x.x. The address 172.20.4.5 falls inside the second. 172.32.0.1, 192.169.1.1 and 11.0.0.1 each sit just outside a private block, which is the trap, so they are public.Two guards on patrol use walkie-talkies. Either can speak, but only one at a time while the other listens. Which transmission mode is this?
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Answer: C — Half duplex
Both directions are possible but not together, which is half duplex. Full duplex, as on a telephone, allows both people to speak at once, and simplex allows one fixed direction only.A full adder receives the inputs A = 1, B = 1 and carry-in = 1. What are its Sum and Carry-out?
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Answer: A — Sum 1 and Carry-out 1
The three bits add to 3, which is 11 in binary: the low bit 1 is the Sum and the high bit 1 is the Carry-out. A half adder with only A = 1 and B = 1 would give Sum 0 and Carry 1, the source of the tempting answer Sum 0 and Carry-out 1.In 8-bit two's complement, which decimal value does the bit pattern 11110100 represent?
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Answer: B — -12
The leading bit is 1, so the number is negative. Inverting gives 00001011 (11), adding 1 gives 00001100 (12), so the value is -12. The value -116 reads the pattern as sign-magnitude and 244 reads it as unsigned binary; -11 forgets to add 1.What is the sum of the hexadecimal numbers (A5) and (1B), written in hexadecimal?
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Answer: A — C0
In decimal A5 is 165 and 1B is 27, and 165 + 27 = 192 = 12 × 16 + 0, which is C0. Adding the last digits, 5 + B = 16, gives 0 with a carry of 1, then A + 1 + 1 = C. The value BC results from mishandling the carry out of the last digit.